mirror of
https://gitdl.cn/https://github.com/chakralinux/core.git
synced 2025-02-03 12:47:16 +08:00
89 lines
3.2 KiB
Diff
89 lines
3.2 KiB
Diff
Intel TSX is broken on Haswell based processors (erratum HSD136/HSW136)
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and a microcode update is available to simply disable the corresponding
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instructions.
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While the responsability to continue or not using TSX should be left to
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the users, a live microcode update will disable the TSX instructions
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causing already started binaries to segfault. This patch simply disable
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Intel TSX (HLE and RTM) on processors which might receive a microcode
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update, so that it doesn't happen. We might expect newer steppings to
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fix the issue, and if it is not the case the corresponding processors
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will be shipped with TSX already disabled.
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Author: Henrique de Moraes Holschuh <hmh@debian.org>
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diff --git a/sysdeps/x86_64/multiarch/init-arch.c b/sysdeps/x86_64/multiarch/init-arch.c
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index db74d97..6f61ae6 100644
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--- a/sysdeps/x86_64/multiarch/init-arch.c
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+++ b/sysdeps/x86_64/multiarch/init-arch.c
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@@ -26,7 +26,7 @@ struct cpu_features __cpu_features attribute_hidden;
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static void
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-get_common_indeces (unsigned int *family, unsigned int *model)
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+get_common_indeces (unsigned int *family, unsigned int *model, unsigned int *stepping)
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{
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__cpuid (1, __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax,
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__cpu_features.cpuid[COMMON_CPUID_INDEX_1].ebx,
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@@ -36,6 +36,7 @@ get_common_indeces (unsigned int *family, unsigned int *model)
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unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
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*family = (eax >> 8) & 0x0f;
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*model = (eax >> 4) & 0x0f;
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+ *stepping = eax & 0x0f;
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}
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@@ -47,6 +48,7 @@ __init_cpu_features (void)
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unsigned int edx;
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unsigned int family = 0;
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unsigned int model = 0;
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+ unsigned int stepping = 0;
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enum cpu_features_kind kind;
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__cpuid (0, __cpu_features.max_cpuid, ebx, ecx, edx);
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@@ -56,7 +58,7 @@ __init_cpu_features (void)
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{
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kind = arch_kind_intel;
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- get_common_indeces (&family, &model);
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+ get_common_indeces (&family, &model, &stepping);
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unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
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unsigned int extended_family = (eax >> 20) & 0xff;
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@@ -131,7 +133,7 @@ __init_cpu_features (void)
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{
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kind = arch_kind_amd;
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- get_common_indeces (&family, &model);
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+ get_common_indeces (&family, &model, &stepping);
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ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;
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@@ -179,6 +181,14 @@ __init_cpu_features (void)
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}
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}
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+ /* Disable Intel TSX (HLE and RTM) due to erratum HSD136/HSW136
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+ on Haswell processors, to work around outdated microcode that
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+ doesn't disable the broken feature by default */
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+ if (kind == arch_kind_intel && family == 6 &&
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+ ((model == 63 && stepping <= 2) || (model == 60 && stepping <= 3) ||
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+ (model == 69 && stepping <= 1) || (model == 70 && stepping <= 1)))
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+ __cpu_features.cpuid[COMMON_CPUID_INDEX_7].ebx &= ~(bit_RTM | bit_HLE);
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+
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__cpu_features.family = family;
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__cpu_features.model = model;
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atomic_write_barrier ();
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diff --git a/sysdeps/x86_64/multiarch/init-arch.h b/sysdeps/x86_64/multiarch/init-arch.h
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index 793707a..e2745cb 100644
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--- a/sysdeps/x86_64/multiarch/init-arch.h
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+++ b/sysdeps/x86_64/multiarch/init-arch.h
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@@ -41,6 +41,7 @@ #define bit_FMA4 (1 << 16)
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/* COMMON_CPUID_INDEX_7. */
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#define bit_RTM (1 << 11)
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+#define bit_HLE (1 << 4)
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#define bit_AVX2 (1 << 5)
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/* XCR0 Feature flags. */
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